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K4S64323LF-S(D)G/S
CMOS SDRAM
2Mx32 Mobile SDRAM 90FBGA
(VDD/VDDQ 2.5V/1.8V or 2.5V/2.5V, PASR & TCSR)
Revision 1.5 December 2002
Rev. 1.5 Dec 2002
K4S64323LF-S(D)G/S
512K x 32Bit x 4 Banks Mobile SDRAM
FEATURES
* * * * 2.5V Power Supply. LVCMOS compatible with multiplexed address. Four banks operation. MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). EMRS cycle with address key programs. All inputs are sampled at the positive going edge of the system clock . Burst read single-bit write operation. Special Function Support. -. PASR (Partial Array Self Refresh). -. TCSR (Temperature Compensated Self Refresh). DQM for masking. Auto & self refresh. 64ms refresh period (4K cycle). Extended temperature range : (-25C to 85 C). 90balls FBGA( -SXXX -Pb, -DXXX -Pb Free).
CMOS SDRAM
GENERAL DESCRIPTION
The K4S64323LF is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.
* * * *
ORDERING INFORMATION
Part No. K4S64323LF-S(D)G/S75 K4S64323LF-S(D)G/S1H K4S64323LF-S(D)G/S1L K4S64323LF-S(D)G/S15 Max Freq. 133MHz(CL=3)*1 105MHz(CL=2) 105MHz(CL=2) 105MHz(CL=3)*2 66MHz(CL=2/3)*3 LVCMOS Interface Package
* * * * *
90FBGA Pb (Pb Free)
FUNCTIONAL BLOCK DIAGRAM
-S(D)S ; Super Low Power, Operating Temp : -25C~85C. -S(D)G ; Low Power, Operating Temp : -25 C~85 C. Notes : 1. In case of 55MHz Frequency, CL1 can be supported. 2. In case of 40MHz Frequency, CL1 can be supported. 3. In case of 33MHz Frequency, CL1 can be supported.
I/O Control
LWE
Data Input Register
LDQM
Bank Select 512K x 32 512K x 32 512K x 32 512K x 32
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
Row Buffer
DQi
Address Register
CLK ADD
Column Decoder Col. Buffer
LRAS
LCBR
Latency & Burst Length
LCKE LRAS LCBR LWE LCAS
Programming Register LWCBR LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.5 Dec 2002
K4S64323LF-S(D)G/S
90-Ball FBGA Package Dimension and Pin Configuration
< Bottom View*1 >
E1 9 A e B C D D E F G D1 H J K D/2 L M N P R E E/2 8 7 6 5 4 3 2 1
CMOS SDRAM
< Top View *2 >
90Ball(6x15) CSP 1 A B C D E F G H J K L M N P R DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 2 DQ24 VDDQ DQ27 DQ29 DQ31 DQM3 A5 A8 CKE NC DQ8 DQ10 DQ12 VDDQ DQ15 3 VSS VSSQ DQ25 DQ30 NC A3 A6 NC A9 NC VSS DQ9 DQ14 VSSQ VSS 7 VD D VDDQ DQ22 DQ17 NC A2 A10 NC BA0 CAS VD D DQ6 DQ1 VDDQ VD D 8 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 BA1 CS WE DQ7 DQ5 DQ3 VSSQ DQ0 9 DQ21 DQ19 VDDQ VDDQ VSSQ VD D A1 NC RAS DQM0 VSSQ VDDQ VDDQ DQ4 DQ2
*2: Top View
Pin Name CLK CS CKE
A A1
Pin Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground [Unit:mm]
A0 ~ A10 BA0 ~ BA1 RAS CAS WE DQM0 ~ DQM3 DQ 0 ~ 31 VDD /VSS VDDQ/VSSQ
Substrate(4Layer)
b
z
*1: Bottom View < Top View*2 >
#A1 Ball Origin Indicator
K4S64323LF-XXXX
SAMSUNG
Week
Symbol A A1 E E1 D D1 e b z
Min 0.30 0.40 -
Typ 1.30 0.35 11.00 6.40 13.00 11.20 0.80 0.45 -
Max 1.40 0.40 0.50 0.10
Rev. 1.5 Dec 2002
K4S64323LF-S(D)G/S
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on V DD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VD D, VDDQ TSTG PD IOS Value -1.0 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150 1 50
CMOS SDRAM
Unit V V C W mA
Notes :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, T = -25C to 85 C) A Parameter Supply voltage Input logic high voltage Input logic low voltage Output logic high voltage Output logic low voltage Input leakage current Symbol VD D VDDQ VIH VIL VOH VOL ILI Min 2.3 1.65 0.8 x V DDQ -0.3 VDDQ-0.2V -10 Typ 2.5 0 Max 2.7 2.7 VDDQ + 0.3 0.3 0.2 10 Unit V V V V V V uA 1 2 IOH = -0.1mA IOL = 0.1mA 3 Note
Notes :
1. VIH (max) = 3.0V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs. 4. Dout is disabled, 0V VOUT VDDQ.
CAPACITANCE
Clock
(VDD = 2.5V, TA = 23C, f = 1MHz, V REF =0.9V 50 mV) Pin Symbol CCLK CIN CADD COUT Min Max 4.0 4.0 4.0 6.0 Unit pF pF pF pF Note
RAS, CAS, WE, CS, CKE, DQM0~ DQM3 Address(A0 ~ A10, BA0 ~ BA1) D Q0 ~ DQ31
Rev. 1.5 Dec 2002
K4S64323LF-S(D)G/S
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25C to 85C) Parameter Symbol Test Condition -75 Burst length = 1 tRC tR C(min) IO = 0 mA CKE VIL(max), tCC = 10ns 70
CMOS SDRAM
Version -1H 70 -1L 65 -15 60
Unit
Note
Operating Current (One Bank Active) Precharge Standby Current in power-down mode
ICC1
mA
1
ICC2P
0.5 0.5 10
ICC2PS CKE & CLK VIL(max), tCC = ICC2 N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns
mA
Precharge Standby Current in non power-down mode
CKE VIH(min), CLK VIL(max), tCC = ICC2NS Input signals are stable ICC3P CKE VIL(max), tCC = 10ns
mA 7 5 5 20 mA
Active Standby Current in power-down mode
ICC3PS CKE & CLK VIL(max), tCC = ICC3 N CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA ,Page burst tRC tR C(min) TCSR Range 4 Banks -S(D)G 2 Banks 1 Bank 4 Banks -S(D)S 2 Banks 1 Bank 85 115 70 110
mA
Active Standby Current in non power-down mode (One Bank Active) Operating Current Refresh Current
ICC3NS ICC4 ICC5
20 70 100 60 80
mA mA mA C 1 2
Max 45C 235 210 195 130 105 90
Max 85C 350 290 270 230 170 150
uA
3
Self Refresh Current
ICC6
CKE 0.2V
uA
4
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. K4S64323LF-S(D)G** 4. K4S64323LF-S(D)S** 5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
Rev. 1.5 Dec 2002
K4S64323LF-S(D)G/S
AC OPERATING TEST CONDITIONS
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition
VDDQ
CMOS SDRAM
(VDD = 2.5V 0.2V, TA = -25 C to 85 C) Value 0.9 x V DDQ / 0.2 0.5 x VDDQ tr/tf = 1/1 0.5 x VDDQ See Fig. 2
Vtt=0.5 x VDDQ
Unit V V ns V
500 Output 500 VOH (DC) = VDDQ -0.2V, IOH = -0.1mA Output VOL (DC) = 0.2V, IOL = 0.1mA 30pF Z0=50
50
30pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)
Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Symbol - 75 tRRD (min) tRCD (min) tRP(min) tRAS(min) tRAS(max) tR C(min) tRDL(min) tDAL (min) tCDL(min) tBDL (min) tCCD (min) CAS latency=3 Number of valid output data CAS latency=2 CAS latency=1 65 70 2 tRDL + tRP 1 1 1 2 1 0 ea 5 15 19 19 45 -1H 19 19 19 50 100 84 90 Version -1L 19 24 24 60 -15 30 30 30 60 ns ns ns ns us ns CLK CLK CLK CLK 1 2,3 3 2 2 4 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode. 4. All parts allow every cycle column address change. 5. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.5 Dec 2002
K4S64323LF-S(D)G/S
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
Parameter CAS latency=3 CLK cycle time CAS latency=2 CAS latency=1 CAS latency=3 CLK to valid output delay CAS latency=2 CAS latency=1 CAS latency=3 Output data hold time CAS latency=2 CAS latency=1 CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS latency=3 CLK to output in Hi-Z CAS latency=2 CAS latency=1 Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. tSHZ tC H tCL tSS tSH tSLZ tOH 2.5 2.5 2.5 2.5 2.0 1.0 1 5.4 7 tSAC tC C Symbol 7.5 9.5 5.4 7 2.5 2.5 3 3 2.5 1.5 1 7 7 1000 - 75 Min Max Min 9.5 9.5 7 7 2.5 2.5 2.5 3 3 2.5 1.5 1 7 8 20 1000 -1H Max Min 9.5 12 25 7 8 20 1000 -1L Max
CMOS SDRAM
- 15 Min 15 15 30 9 9 24 2.5 2.5 2.5 3.5 3.5 3.5 2.0 1 9 9 24 1000 Max
Unit
Note
ns
1
ns
1,2
ns
2
ns ns ns ns ns
3 3 3 3 2
ns
Note : 1. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
Rev. 1.5 Dec 2002
K4S64323LF-S(D)G/S
SIMPLIFIED TRUTH TABLE(V=Valid, X=Dont Care, H=Logic High, L=Logic Low)
COMMAND Register Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit L H H
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1
CMOS SDRAM
A10 /AP
A9 ~ A 0
Note
H H
X H L H X X
L L L H L L
L L H X L H
L L H X H L
L H H X H H
X X
OP CODE X
1, 2 3 3
X X X V V
X Row Address L H L H X V X L H X
Column Address (A0~ A7) Column Address (A0~ A7)
3 3
Bank Active & Row Addr. Read & Column Address Write & Column Address Burst Stop Precharge Bank Selection All Banks Entry Exit Entry Precharge Power Down Mode Exit DQM No Operation Command Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable
4 4, 5 4 4, 5 6
H H H
X X X
L L L H L X H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
Clock Suspend or Active Power Down
H L H
L H L
X X X
X
L H H
H
H L
X X V X X 7
X
H L
X H
X H
X H
X
Notes : 1. OP Code : Operand Code A0 ~ A 10 & BA0 ~ BA1 : Program keys. (@MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are the same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency is 0), but in read operation it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
Rev. 1.5 Dec 2002

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